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? 2008 device engineering incorporated 1 of 13 ds-mw-00429-01 rev. d 9/02/10 figure 1 : bd429 block diagram device engineering incorporated 385 e. alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: admin@deiaz.com bd429/bd429a/bd429b/bd429c arinc 429/rs-422 line driver integrated circuit features: ? arinc 429 line driver for hi speed (100 khz) and low speed (12.5 khz) data rates ? pin for pin replacement part for indu stry standard arinc 429 line drivers ? available in a 16 pin soic (wb), 16 pin cerdip, 16 pin plastic dip, 16 lead ceramic sop, 28l clcc and 28l plcc ? low emi rs-422 line driver mode for data rates up to 100 khz ? adjustable slew rates via two external capacitors ? inputs are ttl and cmos compatible ? low quiescent power of 125mw (typical) ? programmable output differential range via v ref pin ? outputs are fused for failsafe overvoltage protection ? drives full arinc load of 400 ? and 30,000pf ? extended (-55c/+85c) and military (-55c/+125c) te mperature ranges ? 100% final testing
? 2008 device engineering incorporated 2 of 13 ds-mw-00429-01 rev. d 9/02/10 general description: the bd429 arinc line driver circuit is a bipolar monolithic ic designed to meet the requirements of several general aviation serial data bus standards. these include the diffe rential bipolar rz types such as arinc 429, arinc 571, and arinc 575, as well as the differentia l nrz types such as the rs-422 standard. functional description: modes: the bd429 operates in either a 429 mode or a 422 mode as controlled by the 429/422 pin. 429 mode: in 429 mode, the serial data is presented on the data(a) and data(b) inputs in the dual rail format defined in the mark 33 digital information transfer system ? arinc specification 429-10 . the driver is enabled by the sync and clock inputs. the output voltage level is programmed by the v ref input and is normally tied to +5vdc along with v 1 to produce output levels of +5 volts, 0 volts, and ?5 volts on each output for 10 volts differential outputs. * see figure 4 . 422 mode: in 422 mode, the serial data is presented on da ta(a) input. the driver is enabled by the sync and clock inputs. the outputs swings between 0 volts and +5 volts if v ref is at +5vdc. *see figure 5 . output resistance: the driver output resistance is 75 ? 20% at room temperature; 37.5 ? on each output. the outputs are also fused for failsafe protection against shorts to aircraft power. the output slew rate is controlled by external timing capacitors on c a and c b . typical values are 75pf for 100 khz data and 500pf for 12.5 khz data. table 1: truth table
? 2008 device engineering incorporated 3 of 13 ds-mw-00429-01 rev. d 9/02/10 table 2 : pin descriptions pin name description v ref analog input. the voltage on v ref sets the output voltage levels on a out and b out . the output logic levels swing between +v ref , 0 volts, and ?v ref volts. nc no connect sync logic input. logic 0 forces outputs to null state. logic 1 enables data transmission. data(a) data(b) logic inputs. these signals contain the serial da ta to be transmitted on the arinc 429 data bus. refer to figure 4 and figure 5 . c a c b analog nodes. external timing capacitors are ti ed from these points to ground to establish the output signal slew rate. typical c a = c b = 75pf for 100 khz data and c a = c b = 500pf for 12.5 khz data. * a out b out outputs. these are the line driver outputs wh ich are connected to the aircraft serial data bus. -v negative supply input. ?15vdc nominal. gnd ground. +v positive supply input. +15vdc nominal. clock logic input. logic 0 forces outputs to null state. logic 1 enables data transmission. 429/422 ' logic input. mode control for arinc 429 and rs-422 modes. an internal 10k ? pull up resistor keeps the chip in arinc 429 mode when there is no external connection. this creates a default logic 1, enabling the arinc 429 mode. a forced logic 0 enables the rs-422 mode. v 1 logic supply input. +5vdc nominal. * c a and c b pin voltages swing between 5 volts. any electronic switching of the capacitor on the pins must not inhibit the full voltage s wings. fi g ure 2: plcc & clcc pinout figure 3 : dip, soic & csop pinout 7 6 5 4 3 2 1 10 11 12 13 14 15 16 v 1 clock data(b) c b v ref +v gnd -v a out c a data(a) sync nc 9 8 b out nc 429/422' 1282726 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 432 v ref v 1 429/422' nc nc nc nc nc sync a out -v gnd +v b out clock nc nc nc nc nc nc nc nc nc data(a) data(b) c b c a
? 2008 device engineering incorporated 4 of 13 ds-mw-00429-01 rev. d 9/02/10 table 3 : absolute maximum ratings parameter symbol rating units voltage between pins +v and ?v 40 v v 1 maximum voltage v 1 7 v v ref maximum voltage v ref 6 v data(a) max input voltage data(b) max input voltage v data(a) v data(b) (gnd-0.3v) to (v 1 + 0.3v) v lead soldering temperature (10 sec duration) t sld 280 o c storage temperature t stg -65 to +150 o c max junction temperature ceramic package & plastic package short term operation t j max1 +175 o c max junction temperature plastic package limit (prolonged operation) t j max2 +145 o c output short circuit duration see note 1 output over-voltage protection see note 2 power dissipation see table 5 below notes. 1. one output at a time can be shorted to ground indefinitely. 2. both outputs are fused at between 0.5 amp dc a nd 1.0 amp dc to prevent an over-voltage fault from coupling onto the system power bus. table 4 : operating range parameter symbol min typ max units positive supply voltage +v +11.4 16.5 vdc negative supply voltage -v -11.4 -16.5 vdc v 1 v 1 +4.75 +5 +5.25 vdc v ref (for arinc 429) v ref +4.75 +5 +5.25 vdc v ref (for other applications) v ref +3 +6 vdc operating temperature (plastic package) t a -55 +85 c operating temperature (ceramic package) t a -55 +125 c thermal management device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage. proper thermal management is important in designs operating at the hi speed dat a rate (100kbs) with high capacitive loads and high data duty cycles. power dissipation may be estimated from table 5 ?power dissipation table?. device power dissipation (pd) is indicated for 100% data duty cycle with no word gap null times and shou ld be adjusted for the appropriate data duty cycle (dc). pd(application) = dc * [pd(table) - 145mw] + 145mw, where dc is the application data duty cy cle, pd(table) is the pd from the table for the indicated data rate and bus load, and 145 mw is the quiescent power. the application?s data duty cycle (dc) for 100kbs operation is calculated as: dc = (total bits transmitted in 10 sec period / 1,000,000) = (32 x total arinc words transmitted in 10 sec period / 1,000,000). heat transfer from the ic package should be maximized. use maximum trace width on all power and signal connections at the ic. place vias on the signal/power traces close to the ic to maximize heat flow to the internal power planes. if possible, design a solid heat spreader land under and beyond the ic to maximize heat flow from the device.
? 2008 device engineering incorporated 5 of 13 ds-mw-00429-01 rev. d 9/02/10 table 5 : power dissipation table 100% duty cycle, full load = 400 ? /30,000pf half load = 4,000 ? /10,000pf data rate load +v @ 15v -v @ -15v v 1 + v ref @5v bd429 power load power 0 to 100kbps none 2.0ma -5.0ma 4ma 125mw 0.0mw 12.5kbps full 16.0ma 19.0ma 4ma 485mw 60.0mw 100kbps full 48.0ma 51.0ma 4ma 1194mw 325.0mw 12.5kbps half 6.0ma 8.0mw 4ma 196mw 30.0mw 100kbps half 22.0ma 25.0ma 4ma 561mw 162.5mw table 6 : dc electrical characteristics conditions: temperature: -55c to +125c ceramic, -55c to +85c pl astic, +v = +11.4vdc to +16.5vdc, ?v = -11.4vdc to ? 16.5vdc; v 1 = v ref = +5vdc 5%, 429/422' = open circuit (unless otherwise noted.) symbol parameter min typ max unit test conditions iq+v quiescent +v supply current - 2 - ma no load. 429 mode. data = clock = sync = low iq-v quiescent -v supply current - 5 - ma no load. 429 mode. data = clock = sync = low iqv 1 quiescent v 1 supply current - 4 - ma no load. 429 mode. data = clock = sync = low iqv ref quiescent v ref supply current - 10 - a no load. 429 mode. data = clock = sync = low v ih logic 1 input v 2.0 - - v no load. v il logic 0 input v - - 0.6 v no load. i ih logic 1 input i - - 10 a no load. i il logic 0 input i - - -20 a no load. (429/422 pin i il = -2ma max) i ohsc output short circuit current (outpu t high) -80 - - ma short to ground i olsc output short circuit current (output low) 80 - - ma short to ground v oh output voltage high. ( +1) v ref - 250mv v ref v ref + 250mv v no load. 429 mode. v null output voltage null. ( 0 ) -250 - +250 mv no load. 429 mode. v ol output voltage low. ( -1 ) -v ref ? 250mv -v ref -v ref + 250mv v no load. 429 mode. i ct + - timing capacitor charge current c a (+1 ) c b (-1 ) c a (-1 ) c b (+1 ) - +200 ?200 - a a no load. 429 mode. sync = clock = high c a and c b held at zero volts. isc (+v) +v short circuit supply current - - +150 ma output short to ground isc (-v) -v short circuit supply current - - -150 ma output short to ground r out resistance on each output - 37.5 - ? room temp only c in input capacitor - - 15 pf -
? 2008 device engineering incorporated 6 of 13 ds-mw-00429-01 rev. d 9/02/10 ac electrical characteristics figure 4 and figure 5 show the output waveforms for the arinc 429 and rs-422 modes of operation. the output slew rates are controlled by timing capacitors c a and c b . they are charged by 200 a nominal. slew rate (sr) measured as v/ sec, is calculated by: sr = 200/c where c is in pf. data(a) data(b) +v ref +v ref -v ref -v ref a out b out 0v 0v figure 4 : arinc 429 waveforms data(a) +v ref +v ref a out b out 0v 0v figure 5 : rs-422 waveforms
? 2008 device engineering incorporated 7 of 13 ds-mw-00429-01 rev. d 9/02/10 data(a) data(b) a out b out 50% 50% 50% 50% t pnh t pnl 0v 0v figure 6 : propagation delay table 7 : ac electrical characteristics parameter symbol min max units notes output rise time a out or b out c a = c b = 75pf c a = c b = 500pf t r t r 1.0 5.0 2.0 15.0 sec sec output fall time a out or b out c a = c b = 75pf c a = c b = 500pf t f t f 1.0 5.0 2.0 15.0 sec sec input to output propagation delay t pnh t pnl - 3.0 sec see figure 6 below a out / b out skew spec. - - 500 nsec
? 2008 device engineering incorporated 8 of 13 ds-mw-00429-01 rev. d 9/02/10 figure 7: burn in schematic figure 8: typical circuitry ? switching capa citors for high-speed/low-speed operation
? 2008 device engineering incorporated 9 of 13 ds-mw-00429-01 rev. d 9/02/10 table 8 : ordering information dei part number (2) marking (1) package temp range processing bd429 bd429 16 cerdip -55 / +125 c ceramic burn in bd429-g bd429 e3 (1) 16 cerdip g -55 / +125 c ceramic burn in bd429a bd429a 16 soic wb -55 / +85 c plastic standard bd429a-g bd429a e4 (1) 16 soic wb g -55 / +85 c plastic standard bd429a1 bd429a1 16 soic wb -55 / +85 c plastic burn in bd429a1-g bd429a1 e4 (1) 16 soic wb g -55 / +85 c plastic burn in bd429b bd429b 28 plcc -55 / +85 c plastic standard bd429b-g bd429b e3 (1) 28 plcc g -55 / +85 c plastic standard dei0429-nes dei0429-nes 16 pdip -55 / +85 c plastic standard dei0429-nes -g dei0429-nes e3 (1) 16 pdip g -55 / +85 c plastic standard dei0429-nms dei0429-nms 16 pdip -55 / +125 c plastic standard dei0429-wms dei0429-wms 16 csop -55 / +125 c ceramic standard dei0429-wmb dei0429-wmb 16 csop -55 / +125 c ceramic burn in dei0429-ees dei0429-ees 28 lcc -55 / +85 c ceramic standard DEI0429-EMS DEI0429-EMS 28 lcc -55 / +125 c ceramic standard dei0429-emb dei0429-emb 28 lcc -55 / +125 c ceramic burn in notes: 1. all packages marked with lot code and date code. ?e3? or ?e4? after date code denotes pb free category. 2. suffix legend: -xyz: x = package code, y = temperature range code, z = process flow code. table 9 : screening process plastic standard plastic burn in ceramic standard ceramic burn in thermal cycle mil-std-883b m1010.4 cond. b no no 10 cycles 10 cycles gross & fine leak no no yes yes burn in mil-std-883b m1015 cond. a no 160 hrs @ +125 c no 96 hrs @ +125 c electrical test: room temperature 100% 100% 100% 100% high temperature 100% @ +125 c 100% @ +125 c 100% @ +125 c 100% @ +125 c low temperature 0.65% aql@-55c 0.65% aql@-55c 0.65% aql@-55c 0.65% aql@-55c
? 2008 device engineering incorporated 10 of 13 ds-mw-00429-01 rev. d 9/02/10 figure 9: typical transceiver/line driver interconnect configuration table 10: package characteristics package type package ref thermal resist. jc / ja (oc/w) jedec moisture sensitivity level & peak body temp lead finish material / jedec pb-free code pb free designaton jedec mo 16l ceramic dip 16 cerdip 35 / 75 hermetic snpb solder not pb-free ms-030- ac 16l ceramic dip, green 16 cerdip g 35 / 75 hermetic sn solder sn96.5/ag 3/cu 0.5 e3 pb free solder terminals ms-030- ac 16l plastic dip 16 pdip 34 / 70 thru hole snpb solder not pb-free ms-001- bb 16l plastic dip, green 16 pdip g 34 / 77 thru hole sn solder sn96.5/ag 3/cu 0.5 e3 pb free solder terminals ms-001- bb 16l soic wide body 16 soic wb 25 / 75 (4l pcb) msl 2 235oc snpb not pb-free ms-013- aa 16l soic wide body, green 16 soic wb g 25 / 75 (4l pcb) msl 1 260oc nipdau e4 rohs compliant ms-013- aa 16l ceramic sop 16 csop 23 / tbd hermetic au e4 pb free solder terminals na 28l plcc 28 plcc 25 /55 (4l pcb) msl 3 235oc snpb not pb-free ms-018- ab 28l plcc, green 28 plcc g 25 /55 (4l pcb) msl 3 245oc matte sn e3 rohs compliant ms-018- ab 28l ceramic leadless chip carrier 28 lcc 14 / 60 hermetic au e4 pb free solder terminals na
? 2008 device engineering incorporated 11 of 13 ds-mw-00429-01 rev. d 9/02/10 16l cerdip package dimensions 16l soic wb package dimensions 0.100 0.010 (2.54 0.25) 0.020 - 0.070 (0.51 - 1.78) 0.160 max (4.06) 0.060 0.005 (1.52 0.13) 0.018 0.002 (0.46 0.05) 0.125 min (3.18) 0 - 10 deg. 0.385 0.025 (9.78 0.64) 0.008 - 0.012 (0.20 - 0.30) 0.290 - 0.320 (7.37 - 8.13) 0.291 max (7.39) 0.785 max (19.94) 0.025 rad (0.64) 0.050 max (1.27) dimensions are in inches(mm)
? 2008 device engineering incorporated 12 of 13 ds-mw-00429-01 rev. d 9/02/10 28l plcc package dimensions 16l pdip package dimensions
? 2008 device engineering incorporated 13 of 13 ds-mw-00429-01 rev. d 9/02/10 16l csop package dimensions 28 clcc package dimensions dei reserves the right to make changes to any products or speci fications herein. dei makes no warranty, representation, or gua rantee regarding suitability of its products for any particular purpose. 28 1

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